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Wireless Components
ASK Single Conversion Receiver TDA 5201 Version 1.5
Specification July 2004
Revision History Current Version: 1.5 as of 01.07.04 Previous Version: 1.4, March 2000 Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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Edition 07.04 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG July 2004. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
TDA 5201
Product Info
Product Info
General Description The IC is a very low power consump- Package tion single chip ASK Single Conversion Receiver for receive frequencies between 310 and 350MHz. The Receiver offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
Features
s
Low supply current (Is = 4.6mA typ.) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -110dBm
s
Selectable frequency ranges around 315 MHz and 345 MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
s s
s s
s
s
s
s
Application
s s
Keyless Entry Systems Remote Control Systems
s s
Fire Alarm Systems Low Bitrate Communication Systems
Ordering Information
Type TDA 5201 available on tape and reel Ordering Code Q67037-A1118 Package P-TSSOP-28-1
Wireless Components
Product Info
Specification, July 2004
1
2.1 2.2 2.3 2.4
Table of Contents
i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 2 2 3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 3 9 10 10 10 10 11 11 11 11 12 12
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2
4.2 4.3 4.4 4.5
Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 5 6 7
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 2 3 4 8 9 11 13
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 5.5 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5201
Product Description
2.1 Overview
The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency bands 315 and 345MHz. The SHR offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
s s s s
Keyless Entry Systems Remote Control Systems Fire Alarm Systems Low Bitrate Communication Systems
2.3 Features
s s s s s s s s s s
Low supply current (Is = 4.6mA typ.) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ.) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -110dBm Selectable receive frequency bands 315 and 345MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
Wireless Components
2-2
Specification, July 2004
TDA 5201
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2-3
Specification, July 2004
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
TDA 5201
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI MIX AGND FSEL IFO DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CRST2 PDWN PDO DATA 3VOUT THRES FFB OPP SLN SLP LIMX LIM CSEL LF
TDA 5201
22 21 20 19 18 17 16 15
Pin_Configuration_5201_V1.4.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Specification, July 2004
TDA 5201
Functional Description
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4.15V
1
50uA
2 3
VCC LNI
5V Supply LNA Input
57uA
3
500uA 4k
1k
Wireless Components
3-3
Specification, July 2004
TDA 5201
Functional Description
4
TAGC
4.3V
AGC Time Constant Control
3uA 4
1k
1.4uA
1.7V
5 6
AGND LNO
5V
Analogue Ground Return LNA Output
1k
6
7 8
VCC MI
1.7V
5V Supply Mixer Input
2k
2k
9
MIX
8 9
Complementary Mixer Input
400uA
10 11
AGND FSEL
Analogue Ground Return not applicable - has to be left open
Wireless Components
3-4
Specification, July 2004
TDA 5201
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2.2V
60 12
4.5k
13 14 15
DGND VDD LF
5V 4.6V
Digital Ground Return 5V Supply (PLL Counter Circuitry) PLL Filter Access Point
30uA 200 15 100
30uA
2.4V
16
CSEL
5.xx or 10.xx MHz Quartz Selector
1.2V
80k 16
Wireless Components
3-5
Specification, July 2004
TDA 5201
Functional Description
17
LIM
2.4V
Limiter Input
15k 17
18
LIMX
75uA
Complementary Limiter Input
330
18
15k
19
SLP
Data Slicer Positive Input
15uA
100 19
3k
40uA
20
SLN
Data Slicer Negative Input
5uA
10k 20
Wireless Components
3-6
Specification, July 2004
TDA 5201
Functional Description
21
OPP
OpAmp Noninverting Input
5uA
200 21
22
FFB
Data Filter Feedback Pin
5uA
100k 22
23
THRES
AGC Threshold Input
5uA
10k 23
24
3VOUT
24
3V Reference Output
3V
25
DATA
Data Output
200 25 80k
Wireless Components
3-7
Specification, July 2004
TDA 5201
Functional Description
26
PDO
Peak Detector Output
200 26
27
PDWN
27
Power Down Input
220k
220k
28
CRST2
External Crystal Connector 2
4.15V
28
50uA
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3-8
Specification, July 2004
TDA 5201
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
LNO 6 3
MI 8
MIX IFO 9 12
LIM 17
LIMX 18
FFB 22
OPP 21
SLP 19
SLN 20 25 DATA
RF
LNA
RSSI
SLICER
TAGC 4
26 23
PDO THRES
TDA 5201
VDD 14 : 1/2 DGND 13 Loop Filter VCO : 128/64 DET Crystal OSC
AGC Reference
24
3VOUT
UREF
Bandgap Reference
2/7 VCC
5/10 AGND
11 FSEL
15 LF
16 CSEL
1
28
27 PDWN
Crystal
Function_5200.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3-9
Specification, July 2004
TDA 5201
Functional Description
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO was designed to guarantee over production spread and the specified temperature range a receive frequency range between 310 and 350MHz depending on whether high- or low-side injection of the local oscillator is used. The oscillator signal is fed both to the synthesiser divider chain and to a divider that is dividing
Wireless Components
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Specification, July 2004
TDA 5201
Functional Description
the signal by 2 before it is applied to the downconverting mixer. Local oscillator high side injection has to be used for receive frequencies between approximately 310 and 330 MHz, low side injection for receive frequencies between 330 and 350MHz - see also Section 4.4..
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 5 and 10MHz range as the overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States CSEL Open Shorted to ground Crystal Frequency 5.xx MHz 10.xx MHz
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is expained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80dB that has a bandpass-characteristic centred around 10.7MHz. It has an input impedance of 330 to allow for easy interfacing to a 10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4-2. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to turn down the LNA gain by approximately 18dB in case the input signal strength is too strong as described in Section 3.4.1 and Section 4.1.
3.4.6
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
Wireless Components
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Specification, July 2004
TDA 5201
Functional Description
3.4.7
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of approximately 120kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for the detector. The self-adjusting threshold on pin 20 its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.8
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The output can be used as an indicator for the signal strength and also as a reference for the data slicer. The maximum output current is 500A.
3.4.9
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA.
Table 3-3 PDWN Pin Operating States PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
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Specification, July 2004
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
TDA 5201
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R4
R5
Uthreshold
Pins:
24
23 RSSI (0.8 - 2.8V) +3V
OTA
VCC
Iload RSSI > Uthreshold: Iload=4.2A RSSI < Uthreshold: Iload= -1.5A 4 UC C Gain control voltage
LNA
Uc:< 2.6V : Gain high Uc:> 2.6V : Gain low Ucmax= VCC - 0.7V Ucmin = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage.
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Specification, July 2004
TDA 5201
Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1 LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50A, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. R4 can be chosen as 120k, R5 as 180k to yield an overall 3VOUT output current of 10A. Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation a voltage lower than 0.7V shall be applied to the THRES, such as a short to ground. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.
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Specification, July 2004
TDA 5201
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
C1 =
2Q b R 2f 3dB
b 4QRf 3dB
C2 =
with
Q=
the quality factor of the poles where in case of a Bessel filter and thus
b a
a = 1.3617, b = 0.618 Q = 0.577
and in case of a Butterworth filter and thus
a = 1.141, b = 1 Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, July 2004
TDA 5201
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5200
Pin 1
Quartz_load.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1 1 + 2 f X L Cl
with Cl the load capacitance (refer to the quartz crystal specification). Examples: 5.1 MHz: 10.18 MHz: CL = 12 pF CL = 12 pF XL=580 XL=870 CS = 9.8 pF CS = 7.2 pF
These values may be obtained by putting two capacitors in series to the quartz, such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz case. But please note that the calculated value of CS includes the parasitic capacitors also.
Wireless Components
4-5
Specification, July 2004
TDA 5201
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is wide enough to guarantee a receive frequency range between 310 and 350MHz. The VCO signal is divided by 2 before applied to the mixer . This local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer. High-side injection of the local oscillator has to be used for receive frequencies between 310 and 330 MHz. In this case the local oscillator frequency is calculated by adding the IF frequency (10.7 MHz) to the RF frequency. Low-side injection has to be used for receive frequencies between 330 and 350 MHz. The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. The overall division ratios in the PLL are 64 or 32 depending on whether the CSEL-pin is left open or tied to ground. Therefore the quartz frequency may be calculated by using the following formula:
f QU =
with RF LO QU r .... .... .... ....
f RF - 10.7 r
receive frequency local oscillator (PLL) frequency (RF 10.7) quartz oscillator frequency ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table.
Table 4-1 PLL Division Ratio Dependence on States of CSEL CSEL Ratio r = (fLO/fQU) 64 32
open GND Example:
Addition of 10.7 is used in case of operation the device at 315 MHz, subtraction in case of operation at 345 MHz for instance. This yields the following frequencies: CSEL tied to GND:
f QU = (315 MHz + 10 .7 MHz ) / 32 = 10 .1781 MHz
f QU = (345 MHz - 10 .7 MHz ) / 32 = 10 .4469 MHz
Wireless Components
4-6
Specification, July 2004
TDA 5201
Applications
CSEL open:
f QU = (315 MHz + 10 .7 MHz ) / 64 = 5 .0891 MHz f QU = (345 MHz - 10 .7 MHz ) / 64 = 5 .2234 MHz
Wireless Components
4-7
Specification, July 2004
TDA 5201
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer especially for a coding scheme without DC-content, can be generated in two ways, depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated using an external R-C integrator as shown in Figure 4-5. The time constant TA of the R-C integrator has to be significantly larger than the longest period of no signal change TL within the data sequence. In order to keep distortion low, the minimum value for R is 20k.
R C
Pins:
19
20 Uthreshold
data out 25
data filter data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
Another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
R C R data out 25 Uthreshold
Pins: peak detector
26
19
20
data slicer
data filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4-8
Specification, July 2004
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 5.5 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . 5-13
TDA 5201
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins Vs Tj Ts RthJA VESD -1 -0.3 -40 -40 max 5.5 +125 +150 114 +1 V C C K/W kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
Wireless Components
5-2
Specification, July 2004
TDA 5201
Reference
5.1.2
Operating Range
Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C # Parameter Symbol Limit Values min 1 2 Supply Current Receiver Input Level IS RFin -110 max 5.2 -13 mA dBm fRF = 315MHz @ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
s
Unit
Test Conditions/Notes
L
Item
3 4 5 6 7 8 9
LNI Input Frequency MI/X Input Frequency 3dB IF Frequency Range Powerdown Mode On Powerdown Mode Off Gain Control Voltage, LNA high gain state Gain Control Voltage, LNA low gain state
fRF fMI fIF -3dB PWDNON PWDNOFF VTHRES VTHRES
310 310 5 0 2 2.8 0
350 350 23 0.8 VS VS 0.7V
MHz MHz MHz V V V V
s Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in Section 5.2.
Wireless Components
5-3
Specification, July 2004
TDA 5201
Reference
5.1.3
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. The device performance parameters marked with s are not part of the production test, but verified by design or measured on an Infineon evaluation board as desdribed in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V # Parameter Symbol min Supply Supply Current 1 2 LNA Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) Input impedance, fRF = 315 MHz Input level @ 1dB C.P. fRF=315 MHz Input 3rd order intercept point fRF = 315 MHz LO signal feedthrough at antenna port RFin -112 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
s
Limit Values typ max
Unit
Test Conditions / Notes
L
Item
Supply current, standby mode Supply current
IS PDWN IS
50 4.6
70 5
nA mA
Pin 27 (PDWN) open or tied to 0 V
2 3 4
S11 LNA P1dBLNA IIP3LNA LOLNI
0.895 / -25.5 deg -14 -10 dBm dBm fin = 315 & 317MHz
s
s
s
5
-119
dBm
s
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode 1 2 3 4 Gain fRF = 315 MHz Output impedance, fRF = 315 MHz Voltage Gain Antenna to MI fRF = 315 MHz Noise Figure S21 LNA S22 LNA GAntMI NFLNA 1.577 / 150.3 deg 0.897 / -10.3 deg 21 2 dB dB excluding matching network loss - see Appendix
s s s
Signal Input LNI, VTHRES = GND, low gain mode 1 2 Input impedance, fRF = 315 MHz Input level @ 1dB C. P. fRF = 315 MHz S11 LNA P1dBLNA 0.918 / -25.2 deg -7 dBm matched input
s
s
Wireless Components
5-4
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min Signal Input LNI, VTHRES = GND, low gain mode 3 Input 3rd order intercept point fRF = 315 MHz IIP3LNA -13 dBm fin = 315 & 317MHz
s
Limit Values typ max
Unit
Test Conditions/ Notes
L
Item
Signal Output LNO, VTHRES = GND, low gain mode 1 2 3 Gain fRF = 315 MHz Output impedance, fRF = 315 MHz Voltage Gain Antenna to MI fRF = 315 MHz S21 LNA S22 LNA GAntMI 0.007 / 153.7 deg 0.907 / -10.5 deg 2 dB
s s
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 3 50 V A
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 2.8 3 5 VS-1 VS-1V V V V nA or shorted to Pin 24
s
see chapter 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out ITAGC_in 4.2 1.5 A A RSSI > VTHRES RSSI < VTHRES
MIXER Signal Input MI/MIX (PINS 8/9) 1 2 Input impedance, fRF = 315 MHz Input 3rd order intercept point S11 MIX IIP3MIX 0.954 / -10.9 deg -25 dBm
s
s
Signal Output IFO (PIN 12) 1 2 3 4 Output impedance Conversion Voltage Gain fRF=869 MHz Noise Figure, SSB (~DSB NF+3dB) RF to IF isolation ZIFO GMIX NFMIX ARF-IF 330 +21 13 46 dB dB dB
s
s
Wireless Components
5-5
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min LIMITER Signal Input LIM/X (PINS 17/18) 1 2 3 4 Input Impedance RSSI dynamic range RSSI linearity Operating frequency (3dB points) ZLIM DRRSSI LINRSSI fLIM 5 264 60 330 396 80 dB dB 23 MHz
s s s
Limit Values typ max
Unit
Test Conditions/ Notes
L
Item
1
10.7
DATA FILTER 1 2 3 Useable bandwidth RSSI Level at Data Filter Output SLP RSSI Level at Data Filter Output SLP BWBB
FILT
100 1.1 2.65
kHz V V LNA in high gain RFIN ~-103dBm LNA in high gain. RFIN ~-30dBm
s
RSSIlow RSSIhigh
SLICER Signal Output DATA (PIN 25) 1 2 3 4 5 Useable bandwith Capacitive loading of output LOW output voltage HIGH output voltage Output current BWBB
SLIC
100 20 0
VS-1.3
kHz pF V
s
Cmax
SLIC
VSLIC_L VSLIC_H ISLIC_out
VS-1
VS-0.7 200
V A
Output current =200A
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 3 LOW output voltage HIGH output voltage Load current VSLIC_L VSLIC_H Iload -500 0 VS-1 V V A Static load current must not exceed -500A
4
Leakage current
Ileakage
700
nA
Wireless Components
5-6
Specification, July 2004
TDA 5201
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 2 3 4 5 Operating frequency Input Impedance @ ~5MHz Input Impedance @ ~10MHz Serial Capacity @ ~5MHz Serial Capacity @ ~10MHz fCRSTL Z1-28 Z1-28 CS 5=C1 CS10=C1 5 -760 +j580 -600 +j870 9.3 6.4 11 MHz pF pF fundamental mode, series resonance
s
Limit Values typ max
Unit
Test Conditions/ Notes
L
Item
s
PLL Signal LF (PIN 15) 1 Tuning voltage relative to Vs VTUNE 0.4 1.6 2.4 V
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current PDWN Start-up Time until valid IF signal is detected PWDNO
N
2.8 0 19 1
VS 0.8
V V A mS Depends on the used crystal
PWDNOff IPDWN TSU
PLL DIVIDER Signal CSEL (PIN 16) 1 2 3 fCRSTL range 5.xxMHz fCRSTL range 10.xxMHz Input bias current CSEL VCSEL VCSEL ICSEL 1.4 0 5 4 0.2 V V A CSEL tied to GND or open
s Not part of the production test - either verified by design or measured in an Infineon Evalboard as described in Section 5.2.
Wireless Components
5-7
Specification, July 2004
TDA 5201
Reference
5.2 Test Circuit
The device performance parameters marked with s in Section 5.1.3 were either verified by design or measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDA5101 in an evaluation kit that may be ordered on the INFINEON RKE Webpage www.infineon.com/rke
Infineon Technologies Design Center Graz
TITLE: TDA5200 /-01 /-02 Evaluatio
n Board
Test_circuit.wmf
Figure 5-1
Schematic of the Evaluation Board
Wireless Components
5-8
Specification, July 2004
DATE: Jul.19, 1999
FILE: -10 V 2.0
TDA 5201
Reference
5.3 Test Board Layouts
Figure 5-2
Top Side of the Evaluation Board
Figure 5-3
Bottom Side of the Evaluation Board
Wireless Components
5-9
Specification, July 2004
TDA 5201
Reference
Figure 5-4
Component Placement on the Evaluation Board
Wireless Components
5 - 10
Specification, July 2004
TDA 5201
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5201 at 315MHz without use of a Microchip HCS515 decoder.
Table 5-4 Bill of Materials Ref R1 R2 R3 R4 R5 R6 L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 Q2 F1 X2, X3 X1, X4, S1, S5 S4 IC1 TDA 5201 Value 100k 100k 820k 120k 180k 10k 15nH 12pF 3.3 pF 10pF 6.8pF 100pF 47nF 15nH 100pF 33pF 100pF 10nF 10nF 220pF 47nF 470pF 47nF 18pF 12pF (315 + 10.7MHz)/32 SFE10.7MA5-A 142-0701-801 Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% Toko, PTL2012-F15N0G 0805,COG, 2% 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 5% 1206, X7R, 10% Toko, PTL2012-F15N0G 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, X7R, 10% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 0.1pF 0805, COG, 2% HC49/U, fundamental mode, CL = 12pF, e.g. 434.2 MHz: Jauch Q 10.17813-S11-1323-12-10/20 Murata Johnson 2-pole pin connector 3-pole pin connector, or not equipped Infineon
Wireless Components
5 - 11
Specification, July 2004
TDA 5201
Reference
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5201 in conjunction with a Microchip HCS515 decoder.
Table 5-5 Bill of Materials Addendum Ref R21 R22 R23 R24 R25 C21 C22 IC2 T1 D1 Value 22k 100k 22k 820k 560k 100nF 100nF HCS515 BC 847B LS T670-JL Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 1206, X7R, 10% 1206, X7R, 10% Microchip Infineon Infineon
Wireless Components
5 - 12
Specification, July 2004
TDA 5201
Reference
5.5 Appendix - Noise Figure and Gain Circles
The following gain and noise figure circles were measured utilizing Microlab Stub Stretchers and a HP8514 network analyser. Maximum gain is shown at point 1 at 18.5 dB, minimum noise figure ist 1.9dB at point 2, step size of circles is 0.5dB.
Figure 5-5
Gain and Noise Circles of the TDA5201 at 315 MHz.
Wireless Components
5 - 13
Specification, July 2004
TDA 5201
List of Figures
List of Figures
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and Noise Circles of the TDA5201 at 315 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 9 2 3 4 5 7 7 8 9 9 10 13
Wireless Components
List of Figures - 1
Specification, July 2004
TDA 5201
List of Tables
List of Tables
Table 3-1 Table 3-3 Table 5-1 Table 5-2 Table 5-3 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C . . . . . . . . . Operating Range, Ambient temperature TAMB= -40C ... + 85C . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . 3 12 2 3 4
AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) 5 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) 6 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) 7 Table 5-4 Table 5-5 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12
Wireless Components
List of Tables - 1
Specification, July 2004

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